1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits and, in particular, relates to oxide dielectric materials having reduced oxygen vacancies and methods for providing the same.
2. Description of the Related Art
Dielectric materials are extensively relied upon by the semiconductor industry to form charge storing circuit elements within integrated circuits. For example, a typical capacitor structure within an integrated circuit comprises an insulating dielectric layer sandwiched between a lower and upper conducting electrode. This provides the capacitor structure with a desired capacitance, C, that varies proportionally with the dielectric constant, k, of the dielectric layer and the area, A, of the electrodes. Furthermore, some types of memory devices, such as Dynamic Random Access Memory (DRAM) devices, comprise a plurality of these capacitor structures such that the continued presence or absence of a detectable charge on a single capacitor structure indicates the state of a single memory cell of the memory device.
However, due to the limitations of known manufacturing methods, the typical dielectric layer often suffers from a substantially large concentration of oxygen vacancy defects. In particular, an oxygen vacancy exists whenever the crystal structure of an oxide dielectric is missing an oxygen atom. Unfortunately, the presence of oxygen vacancies within the dielectric causes the dielectric layer to have a decreased dielectric constant as well as a decreased electrical resistance.
Thus, a capacitor structure formed of such a dielectric layer usually provides a decreased capacitance, thereby reducing the charge deposited on the electrodes of the capacitor structure in response to a specific voltage differential applied across it electrodes. Moreover, since relatively large leakage currents flow through the dielectric layer of the capacitor structure, the capacitor structures discharges in a relatively short period of time. Consequently, when used in DRAM devices, such capacitor structures require a relatively high refresh rate and, therefore, lengthen the time required to access data from such devices.
Unfortunately, the problems associated with oxygen vacancies within dielectric materials are becoming more apparent as integrated circuits are formed with increasingly smaller circuit elements. For example, high density DRAM devices requiring a large number of capacitor structures demand the electrodes of each capacitor structure to have a relatively small area. Thus, in order to provide a sufficient capacitance in response to the reduced area, A, of the electrodes, dielectric materials having a relatively large dielectric constant, k, otherwise known as high-k dielectric materials, are required. However, known high-k dielectric materials, such as tantalum pentoxide (Ta2O5), barium strontium titanate (BST), barium titanate (BT) lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT), require the presence of oxygen atoms throughout their crystal structures. Furthermore, the dielectric constant and the electrical resistance of these high-k materials are especially sensitive to the presence of oxygen vacancies. Thus, these capacitor structures are more likely to be formed with an insufficient capacitance for developing a detectable charge as well as an insufficient resistance for maintaining the detectable charge.
To address the problem of oxygen vacancies in dielectric materials, manufacturers often subject DRAM integrated circuits to re-oxidation anneals. For example, DRAM integrated circuits are usually exposed to a first annealing process which heats the integrated circuit in an oxidizing environment subsequent to the deposition of the dielectric material and prior to the deposition of the upper electrode so as to source oxygen atoms to the exposed dielectric material to thereby reduce the concentration of oxygen deficiencies. However, since the oxygen deficiencies are often deeply positioned within the oxide dielectric layer, a relatively large concentration of oxygen deficiencies remain. Furthermore, during the deposition of the upper electrode layer, a substantial portion of the remaining oxygen deficiencies are often drawn toward the upper electrode which often forms an oxygen deficiency-rich interface layer in-between the dielectric layer and the upper electrode. Unfortunately, the formation of this defective interface layer causes the capacitor structure to suffer from a disproportionately small dielectric constant as well as a disproportionately small resistance to leakage current.
In an effort to repair the defective interface layer between the dielectric layer and the upper electrode layer, manufacturers often subject DRAM integrated circuits to a second re-oxidation annealing process in an oxidizing environment subsequent to the deposition of the upper electrode. However, the upper electrode essentially acts as a barrier which inhibits oxygen atoms from diffusing into the underlying dielectric layer. Thus, the effectiveness of the second annealing process is substantially limited.
From the foregoing, therefore, it will be appreciated that there is a need for an improved capacitor structure formed in an integrated circuit. In particular, there is a need for the capacitor structure to include a dielectric material with a reduced concentration of oxygen deficiencies. Furthermore, there is a need for the capacitor structure to have a reduced buildup of oxygen deficiencies at an interface layer between the dielectric material and an upper electrode layer of the capacitor structure. To this end, there is a need for an improved method of depositing the upper electrode above the dielectric material so as to reduce the concentration of oxygen deficiencies throughout the dielectric material.
The aforementioned needs are satisfied by the preferred embodiments of the improved conductor-insulator-conductor (CIC) sandwich of the present invention. In one embodiment, a method of forming an improved CIC sandwich for an integrated circuit is provided. In particular, the method comprises depositing a first conducting layer on the integrated circuit. The method further comprises depositing a first insulating layer in contact with the first conducting layer, wherein the first insulating layer comprises a plurality of oxygen atoms in a structure defining a first concentration of oxygen vacancies. The method further comprises depositing a second conducting layer in contact with the first insulating layer in a strongly oxidizing ambient so as to reduce the concentration of oxygen vacancies in the first insulating layer from the first concentration, wherein reducing the concentration of oxygen vacancies in the first insulating layer provides the first insulating layer with improved electrical characteristics.
In another embodiment, a method of forming a memory cell for a DRAM integrated circuit having an improved CIC sandwich is provided. In particular, the method comprises forming a first transistor gate on a substrate, depositing a first insulating layer over the first transistor gate, and forming a conductive plug that extends from an active region of the first transistor gate through the first insulating layer. The method further comprises forming a structural layer over the first insulating layer, and forming a via that extends into the structural layer so as to expose the conductive plug. The method further comprises depositing a first conducting layer over the structural layer so as to coat the interior surfaces of the via with the first conducting layer and so as to electrically couple the conductive plug with the first conducting layer. The method further comprises depositing a second insulating layer over the first conducting layer, wherein the second insulating layer comprises a plurality of oxygen atoms in a structure defining a first concentration of oxygen vacancies. The method further comprises depositing a second conducting layer over the second insulating layer in a strongly oxidizing ambient so as to source oxygen atoms to the second insulating layer so that the concentration of oxygen vacancies of the second insulating layer is reduced from the first concentration.
In another embodiment, the aforementioned needs are satisfied by an integrated circuit comprising an improved conductor-insulator-conductor (CIC) sandwich. In particular, the CIC sandwich comprises a first conducting layer deposited over the integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer, wherein the first insulating layer comprises a structure having a plurality of oxygen sites partially filled by a plurality of oxygen atoms. Furthermore, the unfilled oxygen sites define a concentration of oxygen vacancies. The CIC sandwich further comprises a second conducting layer deposited over the first insulating layer. The CIC sandwich further comprises an oxygen-rich interface layer interposed between the first insulating layer and the second conducting layer. Specifically, the oxygen-rich interface layer acts as a sink for absorbing oxygen vacancies that migrate from the first insulating layer so as to reduce the buildup of oxygen vacancies at the interface layer and so as to reduce the concentration of oxygen vacancies of the first insulating layer.
From the foregoing, it should be apparent that preferred embodiments of the CIC sandwich and the methods for providing such enable the CIC sandwich to have improved electrical characteristics. In particular, the reduced concentration of oxygen vacancies within the CIC sandwich enable the CIC sandwich to have an increased dielectric constant as well as an increased resistance to leakage current flowing through the CIC sandwich. Thus, the preferred embodiments of the CIC sandwich of the present invention are more suitable for use in charge storing devices than CIC sandwiches known in the art. These and other objects and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.